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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
17
Pin Name
Type
Pin No.Function
BRFP[1]
BRFP[2]
BRFP[3]
BRFP[4]
I/O
E4
G14
R1
P15
Backplane Receive Frame Pulse (BRFP[1:4]).
When the Receive Clock
Master mode is active, BRFP[x] is configured as an output and indicates the
frame alignment or the superframe alignment of the backplane receive
stream, BRPCM[x]. BRFP[x] is updated on the active edge of BRCLK[x].
Receive Clock Master T1 mode:
If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x]
cycle during bit 1 of each 193-bit frame. Optionally, BRFP[x] may pulse high
every second frame to ease the identification of data link bits. If superframe
alignment is desired, BRFP[x] pulses high for one BRCLK[x] cycle during bit
1 of frame 1 of every 12-frame or 24-frame superframe. Optionally, BRFP[x]
may pulse high every second superframe to ease the conversion between SF
and ESF.
Receive Clock Master E1 mode:
If basic frame alignment is desired, BRFP[x] pulses high for one BRCLK[x]
cycle during bit 1 of each 256-bit frame. Optionally, BRFP[x] may pulse high
every second frame to ease the identification of NFAS frames. If multiframe
alignment is desired, BRFP[x] transitions high to mark bit 1 of frame 1 of
every 16-frame signaling multiframe and transitions low following bit 1 of
frame 1 of every 16-frame CRC multiframe. Note that if the signaling and
CRC multiframe alignments are coincident, BRFP[x] pulses high for one
BRCLK[x] cycle every 16 frames.
Receive Clock Slave mode:
When the elastic store is enabled (and Clock Slave mode is active on the
backplane receive side), BRFP[x] is configured as an input and is used to
frame align the backplane receive data to the system frame alignment.
When frame alignment is required, a pulse at least 1 BRCLK[x] cycle wide
must be provided on BRFP[x] a maximum of once every frame (193 bit times
in T1, 256 bit times in E1). BRFP[x] is sampled on the active edge of
BRCLK[x].
When in the Receive Clock Master: Clear Channel or Receive Clock Slave:
H-MVIP mode, BRFP[x] is unused and it is recommended that BRFP[x] be
configured as an input and be connected via an external resistor to ground.
After a reset, BRFP[x] is configured as an input.