![](http://datasheet.mmic.net.cn/330000/PM4354-PI_datasheet_16444274/PM4354-PI_438.png)
RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
423
BTPCM[x] is sampled on the falling edge of BTCLK[x], and the functional timing is described by
Figure 73 with the BTCLK[x] signal inverted.
Figure 74: - Concentration Highway Interface Timing, Example1
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
bit 7 TS 31
bit 2 TS 1
bit 1 TS 1
BTCLK[x]
BTFP[x]
BTPCM[x]
1
2
3
4
5
6
7
8
9
10
11
12
CER = 16
13
14
15
16
17
18
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the
BTIF Configuration register to logic 1. In Figure 74, the BTIF’s DE and FE register bits are set to
logic 0 so that BTPCM[x], BTSIG[x], and BTFP[x] are sampled on the falling edge of BTCLK[x].
CMS is set to logic 0 so that the clock rate is equal to the data rate. BOFF[2:0] is set to ‘b110 so
that the receive clock edge (CER) is equal to 16 (as determined by the table in the BTIF Bit Offset
register description of BOFF[2:0]) and BTPCM[x] (and BTSIG[x]) is sampled 16 clock edges after
BTFP[x] is sampled. TSOFF[6:0] is set to ‘b0000000 so that there is no timeslot offset. In the
above example, if TSOFF[6:0] were set to ‘b0011111, then BTPCM[x] would be sampled an
additional 31 timeslots later, exactly one E1 frame after BTFP[x] was sampled as logic 1. In the
above example, if TSOFF[6:0] were set to ‘b0010111, then BTPCM[x] would be sampled an
additional 23 timeslots later, exactly one T1 frame after BTFP[x] was sampled as logic 1.
Figure 75: - Concentration Highway Interface Timing, Example 2
BTCLK[x]
BTPCM[x]
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
1
2
3
4
5
6
7
8
9
10
11
12
bit 7 TS 31
bit 6 TS 31
bit 5 TS 31
CER = 11
BTFP[x]
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the
BTIF Configuration register to logic 1. In Figure 75, the BTIF’s FE register bit is set to logic 1 so
that BTFP[x] is sampled on the rising edge of BTCLK[x]. The DE register bit is set to logic 0 so
that BTPCM[x] is sampled on the falling edge of BTCLK[x]. CMS is set to logic 1 so that the clock
rate is equal to two times the data rate. BOFF[2:0] is set to ‘b001 so that the receive clock edge
(CER) is equal to 11 (as determined by the table in the BTIF Bit Offset register description of
BOFF[2:0]) and BTPCM[x] is sampled 11 clock edges after BTFP[x] is sampled. TSOFF[6:0] is set
to ‘b0000000 so that there is no timeslot offset.