RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
416
Figure 56: - E1 Receive Clock Slave: H-MVIP Mode
1 2
4
3
5 6 7 8
Timeslot 127
Parity Bit
(if enabled)
Timeslot 0
Timeslot 1
Timeslot 2
Parity Bit
(if enabled)
Timeslot 3
CMVFPB
CMV8MCLK
MVBRD
CASBRD
1 2
4
3
5 6 7 8 1 2
4
3
5 6 7 8
1 2
4
3
5 6 7 8
A B C D
A B C D
Timeslot 4
Parity Bit
(if enabled)
Parity Bit
(if enabled)
1 2
4
3
5 6 7 8 1 2
4
3
5 6 7 8
CMVFPC
The Backplane Receive Interface is programmed for Clock Slave: H-MVIP mode. The required
settings are as follows. The RHMVIPEN bit of the Receive H-MVIP/CCS Enable register is set to
logic 1. In the BRIF Configuration register for each of the four quadrants, the bits are set as
follows: CMODE=1, DE=0, FE=1, CMS=1, RATE[1]=1, RATE[0]=1. In the BRIF Frame Pulse
Configuration register for each of the four quadrants, the bits are set as follows: MAP=0,
FPINV=0, FPMODE=1. In the BRIF Parity/F-bit Configuration register for each of the four
quadrants, the TRI bit is set to logic 1. In register address 033H, TSOFF[6:0]=’b0000000. In
register address 133H, TSOFF[6:0]=’b0000001. In register address 233H,
TSOFF[6:0]=’b0000010. In register address 333H, TSOFF[6:0]=’b0000011. Because the interface
is in clock slave mode, the Receive Elastic Store for each of the four quadrants is enabled by
setting the RXELSTBYP bits of the Receive Options registers to logic 0. Parity checking is
optional and controllable on a per-quadrant basis. For quadrants with parity checking enabled,
MVBRD and CASBRD will carry a parity bit during the first bit of each frame. The values of
unused bits will depend on the exact configuration of the COMET-QUAD, and they will be included
in the parity calculation.
In Figure 55, T1 mode is selected by setting the E1/T1B bit of the Global Configuration register to
logic 0. The T1 timeslot format is summarized in Table 94. In Figure 56, E1 mode is selected by
setting the E1/T1B bit of the Global Configuration register to logic 1. The E1 timeslot format is
summarized in Table 95.
13.3 Backplane Transmit Serial Clock and Data Interface Timing
By convention in the following functional timing diagrams, the first bit transmitted in each channel
shall be designated bit 1 and the last shall be designated bit 8. Each of the Backplane Receive
and Backplane Transmit Master and Clock Modes apply to both T1 and E1 configurations with the
exception of the 2.048MHz T1 Clock Slave Modes.