RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
61
has completed. In this mode, the user must be careful to avoid overruns and underruns. An
interrupt can be generated once the FIFO depth has fallen below a user configured lower
threshold as an indicator for the user to write more data.
Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the
FIFO falls below a lower threshold, when the FIFO is full, or if the FIFO is overrun.
If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is
stuffed into the serial data output. This prevents the unintentional transmission of flag or abort
sequences.
Abort characters can be continuously transmitted at any time by setting a control bit. During
packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit
Data register before the previous byte has been depleted. In this case, an abort sequence is
transmitted, and the controlling processor is notified via the UDRI interrupt.
Before enabling TDPR transmission, the XBOC must first be disabled by programming the XBOC
Code register to an all-ones code.
9.29 Transmit Jitter Attenuator (TJAT)
The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep
FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which allows
bipolar violations to pass through the block uncorrected. The incoming data streams are stored in
a FIFO timed to the transmit clock (either CTCLK or the recovered clock). The respective input
data emerges from the FIFO timed to the jitter attenuated clock (Transmit clock) referenced to
either CTCLK, BTCLK[x], or the recovered clock.
The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz Transmit clock output
transmit clock by adjusting Transmit clock's phase in 1/96 UI increments to minimize the phase
difference between the generated Transmit clock and input data clock to TJAT (either CTCLK or
the recovered clock). Jitter fluctuations in the phase of the input data clock are attenuated by the
phase-locked loop within TJAT so that the frequency of Transmit clock is equal to the average
frequency of the input data clock. For T1 applications, to best fit the jitter attenuation transfer
function recommended by TR 62411, phase fluctuations with a jitter frequency above 5.7 Hz are
attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies
below 5.7 Hz are tracked by the generated Transmit clock. In E1 applications, the corner
frequency is 7.6 Hz. To provide a smooth flow of data out of TJAT, Transmit clock is used to read
data out of the FIFO.
If the FIFO read pointer (timed to Transmit clock) comes within one bit of the write pointer (timed
to the input data clock, CTCLK or RSYNC), TJAT will track the jitter of the input clock. This
permits the phase jitter to pass through unattenuated, inhibiting the loss of data.