RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
46
Alarm Integration
The OOF and the AIS defects are integrated, verifying that each condition has persisted for
104 ms (± 6 ms) before indicating the alarm condition. The alarm is removed when the condition
has been absent for 104 ms (± 6 ms).
The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1-FRMR
counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13
or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS
presence indication increments an interval counter which declares AIS Alarm when 25 valid
intervals have been accumulated. An interval with no valid AIS presence indication decrements
the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This
algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of
a 10-3 mean bit error rate.
The Red alarm algorithm monitors occurrences of OOF over a 4 ms interval, indicating a valid
OOF interval when one or more OOF indications occurred during the interval, and indicating a
valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval
with a valid OOF indication increments an interval counter which declares Red Alarm when 25
valid intervals have been accumulated. An interval with valid INF indication decrements the
interval counter; the Red Alarm declaration is removed when the counter reaches 0. This
algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of
frame alignment occurs.
The E1-FRMR can also be disabled to allow reception of unframed data.
9.9
Receive Elastic Store (RX-ELST)
The Elastic Store (ELST) synchronizes backplane receive frames to the backplane receive clock
and frame pulse (BRCLK[x], BRFP[x]) in the Clock Slave backplane receive modes or to the
common backplane receive H-MVIP clock and frame pulse (CMV8MCLK, CMVFP, CMVFPC) in
H-MVIP modes. The frame data is buffered in a two frame circular data buffer. Input data is
written to the buffer using a write pointer and output data is read from the buffer using a read
pointer.
When the elastic store is being used, if the average frequency of the incoming data is greater than
the average frequency of the backplane clock, the write pointer will catch up to the read pointer
and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer
crosses the next frame boundary. The subsequent backplane receive frame is deleted.
If the average frequency of the incoming data is less than the average frequency of the backplane
clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this
condition a controlled slip will occur when the read pointer crosses the next frame boundary. The
previous backplane receive frame is repeated.
A slip operation is always performed on a frame boundary.