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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
133
Register 032H, 132H, 232H, 332H : BRIF Parity/F-bit Configuration
Bit
Type
Function
Default
Bit 7
R/W
RPTYP
0
Bit 6
R/W
RPTYE
0
Bit 5
R/W
FIXF
0
Bit 4
R/W
FIXPOL
0
Bit 3
R/W
PTY_EXTD
0
Bit 2
Unused
X
Bit 1
R/W
Reserved
0
Bit 0
R/W
TRI
0
This register provides control of data integrity checking on the BRPCM[x] and BRSIG[x] signals of
the receive backplane interface in T1 and E1 mode. (When in Receive Clock Slave: H-MVIP
mode, data integrity checking is performed on MVBRD and CASBRD on a per-quadrant basis.
Each of the four BRIF blocks checks parity over the data streams of its associated quadrant.) A
single parity bit in the first bit position of the frame (the F-bit if in T1 mode) represents parity over
the previous frame (including the undefined bit positions). If a 2.048 Mbit/s backplane rate or
Receive Clock Slave: H-MVIP mode is selected, the parity calculation is performed over all bit
positions, including the undefined positions. Signaling parity is similarly calculated over all bit
positions. Parity checking and generation is not supported when in Nx64Kbit/s mode or when
mapping a 1.544 Mbit/s signal onto a 2.048 Mbit/s backplane in the format where the first 24
timeslots are used, i.e., T1 mode, the RATE[1:0] bits in the BRIF Configuration register are “01”
and the MAP bit in the BRIF Frame Pulse Configuration register is logic 1.
RPTYP:
The receive parity type (RPTYP) bit sets even or odd parity in the receive streams. If RPTYP
is a logic 0, the expected parity value in the first bit position of the frame (the F-bit if in T1
mode) of BRPCM[x] or MVBRD for the quadrant and BRSIG[x] or CASBRD for the quadrant
is even, thus it is a one if the number of ones in the previous frame is odd. If RPTYP is a
logic 1, the expected parity value in the first bit position of the frame of BRPCM[x] or MVBRD
for the quadrant and BRSIG[x] or CASBRD for the quadrant is odd, thus it is a one if the
number of ones in the previous frame is even. RPTYP only has effect if RPRTYE is a logic 1.
RPRTYE:
The RPRTYE bit enables receive parity insertion. When set to logic 1, parity is inserted into
the first bit position of the frame for BRPCM[x] or MVBRD of the quadrant and BRSIG[x] or
CASBRD of the quadrant. When set to logic 0, the first bit position of the frame passes
through transparently.