RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
382
12.10.2 Direct Access Mode
Direct access mode to the TPSC, RPSC, or SIGX is not used in the COMET-QUAD. However,
direct access mode is selected by default whenever the COMET-QUAD is reset. The IND bit
within the TPSC, RPSC, and SIGX Configuration registers must be set to logic 1 after a reset is
applied.
12.10.3 Indirect Access Mode
Indirect access mode is selected by setting the IND bit in the TPSC, RPSC, or SIGX Configuration
register to logic 1. When using the indirect access mode, the status of the BUSY indication bit
should be polled to determine the status of the microprocessor access: when the BUSY bit is
logic 1, the TPSC, RPSC, or SIGX is processing an access request; when the BUSY bit is logic 0,
the TPSC, RPSC, or SIGX has completed the request.
The indirect write programming sequence for the TPSC (RPSC, SIGX) is as follows:
1. Check that the BUSY bit in the TPSC (RPSC) μP Access Status register is logic 0. For the
SIGX, check that the BUSY bit in the Timeslot Indirect Status register is logic 0.
2. Write the channel data to the TPSC (RPSC, SIGX) Channel Indirect Data Buffer register.
3. Write RWB=0 and the channel address to the TPSC (RPSC, SIGX) Channel Indirect
Address/Control register.
4. Poll the BUSY bit until it goes to logic 0. The BUSY bit will go to logic 1 immediately after step
3 and remain at logic 1 until the request is complete.
5. If there is more data to be written, go back to step 1.
The indirect read programming sequence for the TPSC (RPSC, SIGX) is as follows:
1. Check that the BUSY bit in the TPSC (RPSC) μP Access Status register is logic 0. For the
SIGX, check that the BUSY bit in the Timeslot Indirect Status register is logic 0.
2. Write RWB=1 and the channel address to the TPSC (RPSC, SIGX) Channel Indirect
Address/Control register.
3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to logic 1 immediately
after step 2 and remain at logic 1 until the request is complete.
4. Read the requested channel data from the TPSC (RPSC, SIGX) Channel Indirect Data Buffer
register.
5. If there is more data to be read, go back to step 1.