![](http://datasheet.mmic.net.cn/330000/PM4354-PI_datasheet_16444274/PM4354-PI_396.png)
RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
381
122D
123D
124D
125D
126D
127D
7F 72 E5 AC
7F 72 E5 AC
7F 72 E5 AC
7F 72 E5 AC
87 73 05 AC
87 73 05 AC
250D
251D
252D
253D
254D
255D
F4 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
FC 19 A3 AC
The Analog Loss Of Signal feature is available for short haul and ISDN signal levels only. (Other
LOS variants are available via the CDRC Interrupt Status and Alternate Loss of Signal registers.)
For short haul and ISDN signal levels, the receiver monitors if the received signal exceeds a
predefined peak amplitude and the ALOSV bit is set when this condition is not meet. The change
in ALOSV state sets the ALOSI bit and can be enabled to assert the INTB.
The RLPS is able to squelch the data in response to an assertion of ALOS. Since this action is not
mandatory, it is not enabled by default. However it can be desirable to do so in which case data
squelching can be enabled by setting the SQUELCHE register bit to logic 1.
12.9 Using the PRBS Generator and Detector
PRBS patterns may be generated in either the transmit or receive directions, and detected in the
opposite direction, as configured by the RXPATGEN bit of the PRBS Positioning/Control And
HDLC Control registers. The timeslots for PRBS generation and detection are configured by the
UNF_GEN and UNF_DET bits of the PRBS Positioning/Control registers or by the TEST bit in the
each of the TPSC’s and RPSC’s PCM Data Control byte.
12.10 Using the Per-Channel Serial Controllers and SIGX
12.10.1 Initialization
Before the TPSC (RPSC) block can be used, a proper initialization of the internal registers must
be performed to eliminate erroneous control data from being produced on the block outputs. The
output control streams should be disabled by setting the PCCE bit in the TPSC (RPSC)
Configuration register to logic 0. Then, all 96 locations of the TPSC (RPSC) must be filled with
valid data. Finally, the output streams can be enabled by setting the PCCE bit in the TPSC
(RPSC) Configuration register to logic 1.
Before the SIGX Per-Timeslot/Per-Channel Configuration register bits in the indirect registers 40H
through 5FH can be used, a proper initialization of the internal registers must be performed to
eliminate erroneous control data from being produced on the block outputs. The output control
streams should be disabled by setting the PCCE bit in the SIGX Configuration register to logic 0.
Then, all 32 locations in E1 or 24 locations in T1 of the SIGX must be filled with valid data. Finally,
the output streams can be enabled by setting the PCCE bit in the SIGX Configuration register to
logic 1.