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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
422
respectively) on the first frame bit of the superframe. When the FPTYP bit is programmed to logic
0, the BTFP[x] input should pulse high to mark the F-bit of each frame.
In E1 mode, BTFP[x] may be chosen to indicate alignment of every frame or the composite CRC
and Signaling multiframe alignment as shown in Figure 71, by programming the FPTYP bit in the
BTIF Frame Pulse Configuration register.
Figure 72: - T1 Transmit 2.048 MHz Clock Slave : Full T1/E1 Mode
A B C D
A B C D
A B C D
Channel 24
Channel
1
Channel
2
Channel
3
Filler
BTFP[x]
BTCLK[x]
BTPCM[x]
BTSIG[x]
1 2
4
3
5 6 7 8
1 2
4
3
5 6 7 8
1 2
4
3
5 6 7 8
1 2
4
3
5 6 7 8
A B C D
F
Filler
Parity Bit
(if enabled)
The Backplane Transmit Interface is configured for the Clock Slave: Full T1/E1 Mode by
programming the BTIF’s CMODE and FPMODE register bits to logic 1. The 2.048 MHz internally
gapped clock mode is selected by programming RATE[1]=0 and RATE[0]=1 in the BTIF
Configuration register. In Figure 72, BTFP[x] is configured for superframe alignment by writing
FPTYP to logic 1 in the BTIF Frame Pulse Configuration register, so that the BTFP[x] input must
pulse once every 12 or 24 frames (for SF and ESF, respectively) on the first F-bit of the multiframe
to specify superframe alignment, instead of once every frame to specify frame alignment. If
FPTYP is logic 0, the BTFP[x] input should pulse high to mark the F-bit of each frame.
BTSIG[x] should carry the signaling bits for each channel in bits 5, 6, 7 and 8. The T1 or E1
transmitter will insert these signaling bits into the data stream.. If parity checking is enabled, a
parity bit should be inserted on BTPCM[x] and BTSIG[x] in the first bit of each frame. The values
of the BTPCM[x] and BTSIG[x] don’t-care bits are not important, except that they will be used in
the backplane parity check if it is enabled.
Figure 73: - T1/E1 Transmit Clock Slave : Clear Channel Mode
BTCLK[x]
BTPCM[x]
1 2
4
3
5 6 7 8 1 2
4
3
5 6 7 8 1 2
4
3
5 6 7 8 1 2
8
The Backplane Transmit Interface is configured for the Clock Slave: Clear Channel mode by
programming FDIS=1 in the Transmit Framing and Bypass Options register. BTPCM[x] is clocked
in on the rising edge of the BTCLK[x] input. When DE=0 in the BTIF Configuration register,