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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
53
When Receive Clock Slave: H-MVIP mode is enabled a 8.192 Mbit/s H-MVIP backplane transmit
interface multiplexes up to 128 channels from 4 T1s or E1s, up to 128 channel associated
signaling (CAS) channels from 4 T1s or E1s and common channel signaling from up to 4 T1s or
E1s. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse,
CMVFPB, for synchronization.
Using the H-MVIP interface forces the T1 or E1 receiver to operate in synchronous mode,
meaning that elastic stores are used.
The H-MVIP backplane receive data pins are multiplexed with serial data outputs to provide H-
MVIP access to 128 data channels.
The CASBRD H-MVIP signal provides access to the Channel Associated Signaling (CAS) for all of
the 128 data channels. The CAS is time division multiplexed exactly the same way as the data
channels and is synchronized with the H-MVIP data channels. Over a T1 or E1 multi-frame the
four CAS bits per channel are repeated with each data byte. Four stuff bits are used to pad each
CAS nibble (ABCD bits) out to a full byte in parallel with each data byte.
Figure 14:
- Receive Clock Slave: Full T1/E1 with CCS H-MVIP
FRMR
Framer:
Frame Alignment,
Alarm Extraction
RECEIVER
RJAT
Digital Jitter
Attenuator
FRAM
Framer:
Slip Buffer RAM
Receive Data[1:4]
Receive CLK[1:4]
BRCLK[1:4]
BRFP[1:4]
BRPCM[1:4]
BRSIG[1:4]
BRPCM[x], BRSIG[x],
Timed to BRCLK[x]
CCS ELST
Elastic
Store
CMV8MCLK
CMVFPC
CCSBRD
CMVFPB
BRIF
Backplane
Receive
System
Interface
CCSBRD Timed
to CMV8MCLK
ELST
Elastic
Store
In Receive Clock Slave: Full T1/E1 with CCS H-MVIP mode, the elastic store is enabled to permit
the input BRCLK[x] to specify the backplane receive-side timing. The backplane receive data on
BRPCM[x] and signaling BRSIG[x] are bit aligned to the 1.544 MHz or 2.048 MHz backplane
receive clock (BRCLK[x]) and are frame aligned to the backplane receive frame pulse (BRFP[x]).
BRSIG[x] contains the signaling state (ABCD or ABAB) in the lower four bits of each channel.
The H-MVIP interface (CMV8MCLK, CMVFPC, CMVFPB, and CCSBRD) extracts Common
Channel Signaling (CCS) from the 24
th
DS0 in T1 mode and up to 3 timeslots (15, 16, 31) in E1
mode. The H-MVIP interface uses common clocks, CMV8MCLK and CMVFPC, and frame pulse,
CMVFPB, for synchronization.