![](http://datasheet.mmic.net.cn/330000/PM4354-PI_datasheet_16444274/PM4354-PI_64.png)
RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
49
9.14 HDLC Receiver (RDLC)
The RDLC is a microprocessor peripheral used to receive HDLC frames on the T1 4kHz ESF
facility data link, the E1 Sa-bit data link, or in any arbitrary timeslot (T1 or E1).
The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros
on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check
sequence (FCS).
In the address matching mode, only those packets whose first data byte matches one of two
programmable bytes or the universal address (all ones) are stored in the FIFO. The two least
significant bits of the address comparison can be masked for LAPD SAPI matching.
Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a
programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are
detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun.
The Status Register contains bits that indicate the overrun or empty FIFO status, the interrupt
status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status
Register also indicates the abort, flag, and end of message status of the data just read from the
FIFO. On end of message, the Status Register indicates the FCS status and if the packet
contained a non-integer number of bytes.
9.15 Bit Oriented Code Detector (RBOC)
The Bit Oriented Code detection function is provided by the RBOC block. This block detects the
presence of 63 of the possible 64 bit oriented codes transmitted in the T1 Facility Data Link
channel in ESF framing format, as defined in ANSI T1.403 and in TR-TSY-000194. The 64
(111111) is similar to the HDLC flag sequence and is used by the RBOC to indicate no valid code
received.
Th
code
Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting
of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0). BOCs are validated when
repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has
been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the
RBOC Configuration/Interrupt Enable register. The RBOC declares that the code is removed if two
code sequences containing code values different from the detected code are received in a moving
window of ten code periods.
Valid BOC are indicated through the RBOC Interrupt Status register. The BOC bits are set to all
ones (111111) if no valid code has been detected. An interrupt is generated to signal when a
detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits
go to all ones).