![](http://datasheet.mmic.net.cn/330000/PM4354-PI_datasheet_16444274/PM4354-PI_429.png)
RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
414
frame. BRPCM[x] and BRSIG[x] may be configured to carry a parity bit during the first bit of each
frame. The values of the filler bits will depend on the exact configuration of the COMET-QUAD,
and they will be included in the parity calculation.
Figure 52: - Concentration Highway Interface Timing, Example 1
BRCLK[x]
BRFP[x]
BRPCM[x]
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
1
2
3
4
5
6
7
8
9
10
11
12
bit 7 TS 31
bit 6 TS 31
bit 5 TS 31
CER = 3
bit 0 TS 1
Concentration Highway Interface (CHI) timing is configured by setting the BOFF_EN bit of the
BRIF Configuration register to logic 1. In Figure 52, the BRIF’s FE bit is set to logic 0 so that
BRFP[x] is sampled on the falling edge of BRCLK[x]. DE is set to logic 1 so that BRPCM[x] is
updated on the rising edge of BRCLK[x]. CMS is set to logic 0 so that the clock rate is equal to the
data rate. BOFF[2:0] is set to ‘b000 so that the transmit clock edge (CET) is equal to three (as
determined by the table in the register description of BOFF[2:0]) and BRPCM[x] is updated 3 clock
edges after BRFP[x] is sampled. TSOFF[6:0] is set to ‘b0000000 so that there is no timeslot
offset.
Figure 53: - Concentration Highway Interface Timing, Example 2
BRCLK[x]
BRFP[x]
BRPCM[x]
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
1
2
3
4
5
6
7
8
9
10
11
12
bit 7 TS 31
bit 6 TS 31
bit 5 TS 31
CER = 8
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
CHI timing is configured by setting BOFF_EN to a logic 1. In Figure 53, FE is set to logic 1 so that
BRFP[x] is sampled on the rising edge of BRCLK[x]. DE is set to logic 1 so that BRPCM[x] is
updated on the rising edge of BRCLK[x]. CMS is set to logic 1 so that the clock rate is equal to
two times the data rate. BOFF[2:0] is set to ‘b001 so that the transmit clock edge (CET) is equal to
8 (as determined by the table in the register description of BOFF[2:0]) and BRPCM[x] is updated 8
clock edges after BRFP[x] is updated. TSOFF[6:0] is set to ‘b0000000 so that there is no timeslot
offset.