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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
346
value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are
equal to 00H.
Polling Mode:
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The
TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper
Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted
at the end of a packet. The TDPR Lower Interrupt Threshold, LINT[6:0], should be set to such a
value that sufficient warning of an underrun is given. Note that the value of UTHR[6:0] must
always be greater than the value of LINT[6:0] unless both values are equal to 00H. The FULLE,
LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a
periodic polling procedure. The following procedure should be followed to transmit HDLC
packets:
1. Wait until data is available to be transmitted, then go to step 2.
2. Read the TDPR Interrupt Status register.
3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling
the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4
or 5 depending on implementation preference.
4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into
the TDPR Transmit Data register. Go to step 6.
5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the
data into the TDPR Transmit Data register. Go to step 6.
6. If more data bytes are to be transmitted in the packet, then go to step 2.
If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic
1. Go to step 1.
12.5 Using the Internal HDLC Receiver
It is important to note that the access rate to the HDLC Receiver (RDLC) registers is limited by the
rate of the XCLK crystal clock input. Consecutive accesses to the RDLC Status and RDLC Data
registers should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no
faster than 8/10 that of the XCLK clock rate. (In T1 mode with a 2.048 MHz XCLK reference,
accesses should be no faster than XCLK x (193 x 8)/2560.) This time is used by XCLK to sample
the event and update the FIFO status. Instantaneous variations in the XCLK clock frequency (e.g.
jitter in XCLK) must be considered when determining the procedure used to read RDLC registers.
On power up of the system, the RDLC should be disabled by setting the EN bit in the
Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then
be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt