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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
25
Pin Name
Type
Pin No.Function
TXCM[1]
TXCM[2]
TXCM[3]
TXCM[4]
Analog
I/O
C5
D12
P5
N12
Transmit Common Mode (TXCM[1:4]).
This pin is the common mode for
the Transmit analog. It requires a 4.7
μ
F capacitor to analog ground and two
12.7
resistors to the corresponding TXRING and TXTIP.
Receive Line Interface
RXTIP[1]
RXTIP[2]
RXTIP[3]
RXTIP[4]
Analog
Input
C7
D10
P7
N10
Receive Analog Positive Pulse (RXTIP[1:4]).
When the analog receive
line interface is enabled, RXTIP[x] samples the received line pulse signal
from an external isolation transformer. RXTIP[x] is normally connected
directly to the positive lead of the receive transformer secondary.
RVREF[1]
RVREF[2]
RVREF[3]
RVREF[4]
Analog
I/O
A8
C9
T8
P9
Receive Voltage Reference (RVREF[1:4]).
This pin must be connected to
an external RC network consisting of a 100 k
resistor connected in parallel
with a 10 nF capacitor to analog ground.
RXRING[1]
RXRING[2]
RXRING[3]
RXRING[4]
Analog
Input
A7
C10
T7
P10
Receive Analog Negative Pulse (RXRING[1:4]).
When the analog receive
line interface is enabled, RXRING[x] samples the received line pulse signal
from an external isolation transformer. RXRING[x] is normally connected
directly to the negative lead of the receive transformer secondary.
Timing Options Control
XCLK
Input
J13
Crystal Clock Input (XCLK).
This signal provides a stable, global timing
reference for the COMET-QUAD internal circuitry via an internal clock
synthesizer. XCLK is a nominally jitter free clock at 1.544 MHz in T1 mode
and 2.048 MHz in E1 mode.
In T1 mode, a 2.048 MHz clock may be used as a reference. When used in
this way, however, the intrinsic jitter specifications to AT&T TR62411 may not
be met.
CTCLK
Input
L16
Common Transmit Clock (CTCLK).
This input signal can be used as a
reference for the transmit line rate generation. CTCLK may be any multiple of
8 kHz (N x 8 kHz, where 1
≤
N
≤
256) so long as CTCLK has minimal jitter
when divided down to 8 kHz. When the CTCLK frequency differs from the
transmit line rate, the transmit jitter attenuation block (TJAT) must be enabled
to synthesize and jitter attenuate the transmit clock. When the CTCLK
frequency is the same as the transmit line rate, CTCLK is optionally jitter
attenuated by the TJAT. When CTCLK jitter attenuation is enabled, the
CTCLK frequency should be programmed into the TJAT Jitter Attenuation
Divider N1 Control register.
The COMET-QUAD may be configured to ignore the CTCLK input and utilize
the Receive recovered clock or the backplane transmit clock.