RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
ii
9.14
HDLC RECEIVER (RDLC).................................................................................49
9.15
BIT ORIENTED CODE DETECTOR (RBOC)....................................................49
9.16
RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ............................50
9.17
PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION
(PRBS) ...............................................................................................................50
9.18
BACKPLANE RECEIVE SYSTEM INTERFACE (BRIF).....................................50
9.19
BACKPLANE TRANSMIT SYSTEM INTERFACE (BTIF) ..................................54
9.20
TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC)..........................57
9.21
TRANSMIT ELASTIC STORE (TX-ELST) .........................................................58
9.22
T1 BASIC TRANSMITTER (T1-XBAS) ..............................................................58
9.23
E1 TRANSMITTER (E1-TRAN)..........................................................................59
9.24
T1 INBAND LOOPBACK CODE GENERATOR (XIBC).....................................59
9.25
PULSE DENSITY ENFORCER (XPDE).............................................................59
9.26
T1 SIGNALING ALIGNER (SIGA)......................................................................59
9.27
BIT ORIENTED CODE GENERATOR (XBOC)..................................................60
9.28
HDLC TRANSMITTER (TDPR)..........................................................................60
9.29
TRANSMIT JITTER ATTENUATOR (TJAT).......................................................61
9.30
LINE TRANSMITTER.........................................................................................66
9.31
TIMING OPTIONS (TOPS) ................................................................................66
9.32
JTAG TEST ACCESS PORT..............................................................................66
9.33
MICROPROCESSOR INTERFACE ...................................................................66
10
NORMAL MODE REGISTER DESCRIPTION ................................................................68
10.1
NORMAL MODE REGISTER MEMORY MAP...................................................68
11
TEST FEATURES DESCRIPTION................................................................................328
11.1
JTAG TEST PORT ...........................................................................................328
12
OPERATION..................................................................................................................331