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RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
345
packets is transmitted and the FIFO depth is at or below the threshold limit. The user should
watch the FULLI and LFILLI interrupts to prevent overruns and underruns.
TDPR Interrupt Routine:
Upon assertion of INTB, the source of the interrupt must first be identified by reading the COMET-
QUAD Master Interrupt Source register (0BCH) followed by reading the Interrupt Source #2
registers for the quadrants (008H, 108H, 208H, 308H). Once the source of the interrupt has been
identified as the TDPR in use, then the following procedure should be carried out:
1. Read the TDPR Interrupt Status register.
2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted
and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence
and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable
the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register
should be written with any value.
3. If OVRI=1, then the FIFO has overflowed. The packet of which the last byte written into the
FIFO belongs to, has been corrupted and must be retransmitted. Other packets in the FIFO
are not affected. Either a timer can be used to determine when sufficient bytes are available
in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth
is at the lower threshold limit.
If the FIFO overflows on the packet currently being transmitted (packet is greater than 128
bytes long), OVRI is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied,
and then flags are continuously sent until there is data to be transmitted. The FIFO is held in
reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte
of the next packet to be transmitted.
4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written.
When in this state, either a timer can be used to determine when sufficient bytes are available
in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth
is at the lower threshold limit.
If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has
since emptied out some of its data bytes and now has space available in its FIFO for more
data.
5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If
there is more data to transmit, then it should be written to the TDPR Transmit Data register
before an underrun occurs. If there is no more data to transmit, then an EOM should be set
at the end of the last packet byte. Flags will then be transmitted once the last packet has
been transmitted.
If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lower-threshold state
earlier, but has since been refilled to a level above the lower-threshold level. Note that the