![](http://datasheet.mmic.net.cn/330000/PM4354-PI_datasheet_16444274/PM4354-PI_216.png)
RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
201
Register 069H, 169H, 269H, 369H: T1 XPDE Interrupt Enable/Status
Bit
Type
Function
Default
Bit 7
R/W
STUFE
0
Bit 6
R/W
STUFF
0
Bit 5
R
STUFI
X
Bit 4
R
PDV
X
Bit 3
R
Z16DI
X
Bit 2
R
PDVI
X
Bit 1
R/W
Z16DE
0
Bit 0
R/W
PDVE
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
STUFE:
The STUFE bit enables the occurrence of pulse stuffing to generate an interrupt on INTB.
When STUFE is set to logic 1, an interrupt is generated on the occurrence of a bit stuff.
When STUFE is a logic 0, bit stuffing occurrences do not generate an interrupt on INTB.
STUFF:
The STUFF bit enables pulse stuffing to occur upon detection of a violation of the pulse
density rule. Bit stuffing is performed in such a way that the resulting data stream no longer
violates the pulse density rule. When STUFF is set to logic 1, bit stuffing is enabled and the
STUFI bit indicates the occurrence of bit stuffs. When STUFF is a logic 0, bit stuffing is
disabled and the PDVI bit indicates occurrences of pulse density violation. Also, when STUFF
is a logic 0, PCM data passes through XPDE unaltered.
STUFI:
The STUFI bit is valid when pulse stuffing is active. This bit indicates when a bit stuff occurred
to eliminate a pulse density violation and that an interrupt was generated due to the bit stuff (if
STUFE is logic 1). When pulse stuffing is active, PDVI remains logic 0, indicating that the
stuffing has removed the density violation. The STUFI bit is reset to logic 0 once this register
is read. If the STUFE bit is also logic 1, the interrupt is also cleared once this register is read.
PDV:
The PDV bit indicates the current state of the pulse density violation indication. When PDV is
a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the
pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density
violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit