RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
347
will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be
continuously polled to check the interrupt status (INTR) bit.
After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time
by setting the EN bit in the RDLC Configuration register to logic 1. To indicate the timeslot and bits
within the timeslot in which the HDLC message should be received, configure the RXCE Receive
Data Link Control and RXCE Receive Data Link Bit Select registers as desired. When the RDLC
is enabled, it will assume the link status is idle (all ones) and immediately begin searching for
flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written
into the FIFO buffer. This is done to provide alignment of link up status with the data read from
the FIFO. When an abort character is received, another dummy byte and link down status is
written into the FIFO. This is done to provide alignment of link down status with the data read
from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status
register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied
to determine the current link status. The first flag and abort status encoded in the PBS bits is
used to set and clear a Link Active software flag.
When the last byte of a properly terminated packet is received, an interrupt is generated. While
the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the
external processor to empty the bytes remaining in the FIFO or to just increment a number-of-
packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC
Status register is read, the PKIN bit is cleared to logic 0. If the RDLC Status register is read
immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the
CRC and non-integer byte status can be checked by reading the PBS[1:0] bits.
When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to
remove this source of interrupt.
The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the
polled mode, the processor controlling the RDLC must periodically read the RDLC Status register
to determine when to read the RDLC Data register. In the interrupt driven mode, the processor
controlling the RDLC uses the COMET-QUAD INTB output and the COMET-QUAD Master
Interrupt Source registers to determine when to read the RDLC Data register.
In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of
the COMET-QUAD is connected to the interrupt input of the processor. The processor interrupt
service routine verifies what block generated the interrupt by reading the COMET-QUAD Master
Interrupt Source register followed by one of the second level master interrupt source registers to
identify one of the 4 HDLC receivers as the interrupt source. Once it has identified that the RDLC
has generated the interrupt, it processes the data in the following order:
1. Read the RDLC Status register. The INTR bit should be logic 1.
2. If OVR = 1, then discard the last frame and go to step 1. Overrun causes a reset of FIFO
pointers. Any packets that may have been in the FIFO are lost.
3. If COLS = 1, then set the EMPTY FIFO software flag.