RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
vii
FIGURE 25
- TRANSMIT TIMING OPTIONS ...........................................................................91
FIGURE 26: - FER COUNT VS. BER (E1 MODE)...................................................................340
FIGURE 27: - CRCE COUNT VS. BER (E1 MODE)................................................................341
FIGURE 28: - FER COUNT VS. BER (T1 ESF MODE)...........................................................341
FIGURE 29: - CRCE COUNT VS. BER (T1 ESF MODE)........................................................342
FIGURE 30: - CRCE COUNT VS. BER (T1 SF MODE) ..........................................................343
FIGURE 31: - TYPICAL DATA FRAME ....................................................................................349
FIGURE 32: - EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE...............................349
FIGURE 33: - LINE LOOPBACK..............................................................................................383
FIGURE 34: - PAYLOAD LOOPBACK .....................................................................................384
FIGURE 35: - DIAGNOSTIC DIGITAL LOOPBACK.................................................................385
FIGURE 36 - RSYNC GENERATION .....................................................................................386
FIGURE 37: - BOUNDARY SCAN ARCHITECTURE ..............................................................402
FIGURE 38: - TAP CONTROLLER FINITE STATE MACHINE................................................404
FIGURE 39: - INPUT OBSERVATION CELL (IN_CELL) .........................................................407
FIGURE 40: - OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE)...........................408
FIGURE 41: - BIDIRECTIONAL CELL (IO_CELL)...................................................................409
FIGURE 42: - LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS......................409
FIGURE 43: - T1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE ......................................410
FIGURE 44: - E1 RECEIVE CLOCK MASTER : FULL T1/E1 MODE.....................................410
FIGURE 45: - T1 RECEIVE CLOCK MASTER: NX64KBIT/S MODE...................................... 411
FIGURE 46: - E1 RECEIVE CLOCK MASTER : NX64KBIT/S MODE..................................... 411
FIGURE 47: - T1/E1 RECEIVE CLOCK MASTER : CLEAR CHANNEL MODE......................412
FIGURE 48: - T1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE...........................................412
FIGURE 49: - E1 RECEIVE CLOCK SLAVE: FULL T1/E1 MODE...........................................412