RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
420
Figure 68: - E1 Transmit Clock Master: Nx64Kbit/s Mode (DE=0, FE=0)
Timeslot 31
Timeslot 1
1 2
4
3
5 6 7 8
1 2
4
3
5 6 7 8
A B C D
A B C D
BTFP[x]
BTPCM[x]
BTSIG[x]
BTCLK[x]
The BTIF Configuration register is programmed to select Nx64Kbit/s mode. The TPSC PCM Data
Control bytes are programmed to insert the desired channels. In Figure 65 and Figure 67, the
PCM Data Control bytes for T1 channels 1 and 24 are configured to insert BTPCM[x] data into
these channels. In Figure 66 and Figure 68, the PCM Data Control bytes for E1 channels 1 and
31 are configured to insert BTPCM[x] data into these channels. BTCLK[x] is gapped so that it is
only active for those channels with the associated IDLE_CHAN bit cleared (logic 0). The
remaining channels (with IDLE_CHAN set) contain the per-channel idle code as defined in the
associated Idle Code byte.
In Figure 65 and Figure 66, the BTIF’s DE bit is logic 1, indicating that BTPCM[x] and BTSIG[x]
are sampled on the rising edge of BTCLK[x]; the BTIF’s FE bit is logic 0, indicating that BTFP[x]
updates on the falling edge of BTCLK[x]. Since BTFP[x] is an output and DE and FE have
opposite values, BTFP[x] updates three clock edges before where the first bit of the frame would
be sampled (assuming the clock were not gapped). In Figure 67 and Figure 68, the BTIF’s DE bit
is logic 0, indicating that BTPCM[x] and BTSIG[x] are sampled on the falling edge of BTCLK[x];
the BTIF’s FE bit is logic 0, indicating that the BTFP[x] output updates on the falling edge of
BTCLK[x].
The level of the clock gap is determined by the BTIF’s DE bit. If DE is logic 0, the clock gap is
logic 0; if DE is logic 1, the clock gap is logic 1.
If DE and FE were both logic 1, the functional timing is as described in Figure 65 and Figure 66
but with BTFP[x] updating three clock edges later (assuming the clock were not gapped). If DE
were logic 0 and FE logic 1, then the functional timing is as described in Figure 67 and Figure 68
but with BTFP[x] updating three clock edges earlier (assuming the clock were not gapped).
Figure 69: - T1/E1 Transmit Clock Master : Clear Channel Mode
BTCLK[x]
BTPCM[x]
1 2
4
3
5 6 7 8 1 2
4
3
5 6 7 8 1 2
4
3
5 6 7 8 1 2
8
The Backplane Transmit Interface is configured for the Clock Master: Clear Channel mode by
programming the CMODE bit of the BTIF Configuration register to logic 0 and the FDIS bit of the