![](http://datasheet.mmic.net.cn/330000/PM4354-PI_datasheet_16444274/PM4354-PI_60.png)
RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
45
AIS Detection
When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting
the AISD bit of the E1-FRMR Maintenance/Alarm Status register to logic 1 when fewer than three
zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of
512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in
each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit
to be set to logic 0.
Signaling Frame Alignment
Once the basic frame alignment has been found, the E1-FRMR searches for Channel Associated
Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling
multiframe alignment is declared when at least one non-zero timeslot 16 bit is observed to
precede a timeslot 16 containing the correct CAS alignment pattern, namely four zeros (“0000”) in
the first four bit positions of timeslot 16.
Once signaling multiframe alignment has been found, the E1-FRMR sets the OOSMFV bit of the
E1-FRMR Framing Status register to logic 0, and monitors the signaling multiframe alignment
signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the
Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using
debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely
indicated in the presence of a 10-3 bit error rate.
This E1-FRMR also indicates the reception of TS 16 AIS when timeslot 16 has been received with
three or fewer zeros in each of two consecutive multiframe periods. The TS16AIS signal is
cleared when each of two consecutive signaling multiframe periods contain four or more zeros OR
when the signaling multiframe signal is found.
The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe
alignment signals have been received in error, or additionally, if all the bits in timeslot 16 are
logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of CAS multiframe alignment is also
declared if basic frame alignment has been lost.
National Bit Extraction
The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords
Sa4[1:4], Sa5[1:4], Sa6[1:4], Sa7[1:4] and Sa8[1:4]. The corresponding register values are
updated upon generation of the CRC submultiframe interrupt.
This E1-FRMR also detects the V5.2 link ID signal, which is detected when 2 out of 3 Sa7 bits are
zeros. Upon reception of this Link ID signal, the V52LINKV bit of the E1-FRMR Framing Status
register is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones.