RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
411
In Figure 43, a 1.544 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of
the BRIF Configuration register to ‘b00 and the E1/T1B bit of the Global Configuration register to
logic 0. In Figure 44, a 2.048 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0]
bits of the BRIF Configuration register to ‘b01 and the E1/T1B bit of the Global Configuration
register to logic 1.
Figure 45: - T1 Receive Clock Master: Nx64Kbit/s Mode
Channel 24
Channel 2
BRFP[x]
BRCLK[x]
BRPCM[x]
BRSIG[x]
1 2
4
3
5 6 7 8
1 2
4
3
5 6 7 8
A B C D
A B C D
Figure 46: - E1 Receive Clock Master : Nx64Kbit/s Mode
Timeslot 31
Timeslot 1
BRFP[x]
BRCLK[x]
BRPCM[x]
BRSIG[x]
1 2
4
3
5 6 7 8
1 2
4
3
5 6 7 8
A B C D
A B C D
In Figure 45 and Figure 46, the BRIF Configuration register is programmed to select Nx64Kbit/s
mode. The BRIF’s CMS register bit is logic 0, indicating that the BRCLK[x] clock rate is the same
as the BRPCM[x] and BRSIG[x] data rates. The DE and FE register bits are programmed to logic
0, configuring BRPCM[x], BRSIG[x], and BRFP[x] to update on the falling edge of BRCLK[x]. The
BRIF’s CMODE and FPMODE register bits are programmed to logic 0, indicating BRCLK[x] and
BRFP[x] are outputs, respectively. The RPSC backplane receive control bytes are programmed to
extract the desired channels. In Figure 45, the backplane receive control bytes for T1 channels 2
and 24 are extracted. In Figure 46, the backplane receive control bytes for E1 channels 31 and 1
are extracted. BRCLK[x] is gapped so that it is only active for those channels whose associated
DTRKC bit is programmed to logic 0. If either BRXSMFP (ROHM, BRXCMFP, and BRXSMFP in
E1 mode) or ALTBRFP is configured, then BRFP[x] will pulse only during the appropriate frames.
If the DE register bit were programmed to logic 1, BRPCM[x] and BRSIG[x] would update on the
rising edge of BRCLK[x]. If the FE register bit were programmed to logic 1, BRFP[x] would update
on the rising edge of BRCLK[x].