RELEASED
PM4354 COMET-QUAD
DATASHEET
PMC-1990315
ISSUE 6
FOUR CHANNEL COMBINED E1/T1/J1
TRANSCEIVER / FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR ITS CUSTOMERS’ INTERNAL USE
295
PBS[2:0]
Significance
010
The data byte read from the FIFO is the dummy byte that was written into the
FIFO when the HDLC abort sequence (01111111) was detected. This indicates
that the data link became inactive.
011
Reserved
100
The data byte read from the FIFO is the last byte of a normally terminated
packet with no CRC error and the packet received had an integer number of
bytes.
101
The data byte read from the FIFO must be discard because there was a non-
integer number of bytes in the packet.
110
The data byte read from the FIFO is the last byte of a normally terminated
packet with a CRC error. The packet was received in error.
111
The data byte read from the FIFO is the last byte of a normally terminated
packet with a CRC error and a non-integer number of bytes. The packet was
received in error.
PKIN:
The Packet In (PKIN) bit is logic 1 when the last byte of a non-aborted packet is written into
the FIFO. The PKIN bit is cleared to logic 0 after the Status Register is read.
COLS:
The Change of Link Status (COLS) bit is set to logic 1 if the RDLC has detected the HDLC
flag sequence (01111110) or HDLC abort sequence (01111111) in the data. This indicates that
there has been a change in the data link status. The COLS bit is cleared to logic 0 by reading
this register or by clearing the EN bit in the Configuration Register. For each change in link
status, a byte is written into the FIFO. If the COLS bit is found to be logic 1 then the FIFO
must be read until empty. The status of the data link is determined by the PBS bits associated
with the data read from the FIFO.
OVR:
The overrun (OVR) bit is set to logic 1 when data is written over unread data in the FIFO
buffer. This bit is not reset to logic 0 until after the Status Register is read. While the OVR bit
is logic 1, the RDLC and FIFO buffer are held in the reset state, causing the COLS and PKIN
bits to be reset to logic 0.
FE:
The FIFO buffer empty (FE) bit is set to logic 1 when the last FIFO buffer entry is read. The
FE bit goes to logic 0 when the FIFO is loaded with new data.