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参数资料
| 型号： | SCD223110QCD |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 2 CHANNEL(S), 256K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封装： | METRIC, QFP-100 |
| 文件页数： | 131/178页 |
| 文件大小： | 2247K |
| 代理商： | SCD223110QCD |
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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
56
Datasheet
The CPU has the following five options:
1. Terminate the buffer.
2. Discard the exception.
3. Terminate the buffer and discard the exception.
4. Continue from the current position in the buffer.
5. Leave an ‘n’ byte gap in the buffer and then continue.
The required option is written to the REOIR (Receive End-of-Interrupt register) by the CPU to
terminate the interrupt. If the terminate buffer option is chosen, the 2231own bit in the ARBSTS/
BRBSTS register should first be cleared by the CPU, or a new buffer can be supplied by the CPU.
5.4.9.1
Receive Timeout in Asynchronous DMA Mode
In Asynchronous DMA mode, the only way that the CD2231 releases the ownership is by reaching
the end-of-buffer. Receive timeout, or any exceptions, do not release the ownership if end-of-buffer
condition is not met. The following illustrates recommended procedures to handle a receive
timeout in Asynchronous DMA mode.
Scenario 1: Buffer A is currently selected, receive timeout occurs, host wants to continue on.
Recommendation: Do nothing in the receive timeout interrupt service routine.
Scenario 2: Buffer A is currently selected, receive timeout occurs, host no longer requires DMA.
Recommendation: Reset ownership bits in ARBSTS/BRBSTS, and set TermBuff in REOIR in the
receive timeout interrupt service routine.
Scenario 3: Buffer A is currently used, receive timeout occurs, host wants to start DMA in Buffer
B.
Recommendation: Set TermBuff in REOIR in the receive timeout interrupt service routine. The
CD2231 switches to Buffer B.
Note:
When a receive timeout occurs in Buffer B, the CD2231 pops back to Buffer A, unless the host
clears both Ownership Status bits.
The above scenarios applies if Buffer B is selected first.
5.4.9.2
Receive Bus Errors
When a receive bus error interrupt is generated, the RISR and ARBSTS/BRBSTS registers indicate
a bus error status. The current transfer address is available in RCBADR[0–3], the bus error
occurred on the last transfer that started at this address. This means that the actual error address can
be up to 16 bytes further in the buffer.
Following a bus-error condition, the CPU can either discontinue the current buffer or retry from the
start of the last transfer. If the buffer is to be discontinued, the number of valid receive bytes can be
calculated by subtracting the starting address A/BRBADR[0–3] from the current address
RCBADR[0–3]. The CPU should set the TermBuff bit in REOIR to terminate this buffer and move
to the next.
The transfer that failed to the first buffer, due to the bus error, is still in the receive FIFO and is
transferred to the next buffer following the end of interrupt.
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