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参数资料
型号： SCD223110QCD
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 2 CHANNEL(S), 256K bps, SERIAL COMM CONTROLLER, PQFP100
封装： METRIC, QFP-100
文件页数： 42/178页
文件大小： 2247K
代理商： SCD223110QCD
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
136
Datasheet
8.5.3.5
Transmit Data Register (TDR)
This register accesses the transmit data FIFO of a channel, interrupting for transmit data transfer.
This register address is used for all channels to transfer transmit FIFO data to the host, if
programmed in Interrupt Transfer mode. Data must be written as bytes, and follows the rules listed
in Section 7.4 for positioning valid data on the bus. If the BYTESWAP pin is high, data must be
valid on A/D[0–7]; if BYTESWAP is low, data must be valid on A/D[8–15] because the TDR is on
an even address.
8.5.3.6
Transmit End of Interrupt Register (TEOIR)
The Transmit End of Interrupt register must be written to by the corresponding host interrupt
service routine to signal to the CD2231 that the current interrupt service is concluded. This must be
the last access to the CD2231 during an interrupt service routine. Writing to this register generates
an internal end of interrupt signal which pops the CD2231 interrupt context stack.
Depending on the circumstances of an individual interrupt service, the host can be required to pass
a parameter to the CD2231 through these registers.
Bit 7
1 = Terminate buffer in DMA mode forces the current buffer to be discarded.
Note:
If current interrupt is a transmit end-of-buffer interrupt, setting this bit at the end of the service
routine causes the next buffer to be terminated also.
Bit 6
End of frame in Synchronous modes using interrupt-driven data transfer
0 = this data transfer does not complete the frame/block.
1 = this data transfer does complete the frame/block.
Bit 5
Set General Timer 2 in Synchronous modes
0 = do not set General Timer 2.
1 = load the value, provided in TISR, to General Timer 2.
Bit 4
Set General Timer 1 in Synchronous modes
0 = do not set General Timer 1.
1 = load the value, provided in TISR, to the high byte of General Timer 1.
Register Name: TDR
Register Description: Transmit Data
Default Value: x’00
Access: Byte Write Only
Intel Hex Address: x’F8
Motorola Hex Address: x’F8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
Register Name: TEOIR
Register Description: Transmit End of Interrupt
Default Value: x’00
Access: Byte Write only
Intel Hex Address: x’86
Motorola Hex Address: x’85
Bit 7Bit 6Bit 5Bit 4Bit 3
Bit 2Bit 1
Bit 0
TermBuff
EOF
SetTm2
SetTm1
Notrans
0
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