参数资料
型号: SCD223110QCD
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), 256K bps, SERIAL COMM CONTROLLER, PQFP100
封装: METRIC, QFP-100
文件页数: 43/178页
文件大小: 2247K
代理商: SCD223110QCD
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Datasheet
137
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in the Transmit Interrupt Status register. When the timer reaches ‘0’, the
CD2231 generates a modem/timer group interrupt to the host.
Bit 3
No transfer of data
This bit must be set by the host, if no data is transferred to the transmit FIFO during
a data transfer interrupt.
Bits 2:0
Reserved – must be ‘0’.
8.5.4
Modem Interrupt Registers
8.5.4.1
Modem Priority Interrupt Level Register (MPILR)
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2231 interrupt types (modem, transmit, or
receive) is being acknowledged when IACKIN* is asserted. The CD2231 compares bits 0–6 in this
register with A[6:0] to determine if the acknowledge level is correct. The value programmed in the
MSB of this register has no effect on the IACK cycle.
The MPILR must contain the code used to acknowledge modem/timer interrupts.
Note:
Bit 7 of this register is always read back as ‘0’. When each of the three Priority Interrupt Level
registers is programmed with the same value, they are internally prioritized, with receive as the
highest priority, followed by transmit and modem.
8.5.4.2
Modem Interrupt Register (MIR)
Bit 7
Mer
Modem enable is set by the CD2231 to initiate a modem interrupt request sequence.
It is cleared during a valid modem interrupt acknowledge cycle.
Bit 6
Mact
Modem active is set automatically when Men is set, and the Fair Share logic allows
Register Name: MPILR
Register Description: Modem Priority Interrupt Match
Default Value: x’00
Access: Byte Read/Write
Intel Hex Address: x’E1
Motorola Hex Address: x’E3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-assigned priority match value
Register Name: MIR
Register Description: Modem Interrupt
Default Value: x’00
Access: Byte Read only
Intel Hex Address: x’ED
Motorola Hex Address: x’EF
Bit 7
Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Men
Mact
Meo
0
Mvct [1]
Mvct [0]
0
Mcn [0]
相关PDF资料
PDF描述
SCDV5540 5X5 DOT MATRIX DISPLAY, RED, 3.2 mm
SCDV5541 5X5 DOT MATRIX DISPLAY, YELLOW, 3.2 mm
SCDV5543 5X5 DOT MATRIX DISPLAY, GREEN, 3.2 mm
SCF5249LAG120 32-BIT, 120 MHz, RISC PROCESSOR, PQFP144
SCF5250CAG120 32-BIT, 120 MHz, MICROPROCESSOR, PQFP144
相关代理商/技术参数
参数描述
SCD224K122A324F 制造商:Cornell Dubilier Electronics 功能描述:FILM CAPACITOR
SCD224K122A3Z25 制造商:Cornell Dubilier Electronics 功能描述:Cap Film 0.22uF 1200V PP 10% (46.99 X 24.6 X 24.1mm) Screw Mount
SCD224K122A3Z25-F 功能描述:薄膜电容器 1200Vdc .22uF 580Vac RoHS:否 制造商:Cornell Dubilier 产品类型: 电介质:Polyester 电容:0.047 uF 容差:10 % 电压额定值:100 V 系列:225P 工作温度范围:- 55 C to + 85 C 端接类型:Radial 引线间隔:9.5 mm
SCD224K162A3-24 制造商:Cornell Dubilier Electronics 功能描述:FILM CAPACITOR
SCD224K162A324F 制造商:Cornell Dubilier Electronics 功能描述:FILM CAPACITOR