参数资料
型号: SCD223110QCD
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), 256K bps, SERIAL COMM CONTROLLER, PQFP100
封装: METRIC, QFP-100
文件页数: 8/178页
文件大小: 2247K
代理商: SCD223110QCD
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Datasheet
105
8.2.12
Receive Frame Address Registers — HDLC Sync Mode Only
8.2.12.1
Receive Frame Address Register 1 (RFAR1)
8.2.12.2
Receive Frame Address Register 2 (RFAR2)
8.2.12.3
Receive Frame Address Register 3 (RFAR3)
8.2.12.4
Receive Frame Address Register 4 (RFAR4)
Reception of an HDLC frame can be qualified with a matched 1- or 2-byte address field either as
four 1-byte alternatives or two 2-byte alternatives. The use of RFAR registers for address
recognition is described in the Channel Option registers (COR1) on page 90.
Register Name: RFAR1
Register Description: Receive Frame Address Register 1
Default Value: x’00
Access: Byte Read/Write
Intel Hex Address: x’1C
Motorola Hex Address: x’1F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frame Qualification Address 1
Register Name: RFAR2
Register Description: Receive Frame Address Register 2
Default Value: x’00
Access: Byte Read/Write
Intel Hex Address: x’1D
Motorola Hex Address: x’1E
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frame Qualification Address 2
Register Name: RFAR3
Register Description: Receive Frame Address Register 3
Default Value: x’00
Access: Byte Read/Write
Intel Hex Address: x’1E
Motorola Hex Address: x’1D
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frame Qualification Address 3
Register Name: RFAR4
Register Description: Receive Frame Address Register 4
Default Value: x’00
Access: Byte Read/Write
Intel Hex Address: x’1F
Motorola Hex Address: x’1C
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frame Qualification Address 4
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