参数资料
型号: SCD223110QCD
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), 256K bps, SERIAL COMM CONTROLLER, PQFP100
封装: METRIC, QFP-100
文件页数: 4/178页
文件大小: 2247K
代理商: SCD223110QCD
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Datasheet
101
Bits 2:0
Parity/framing error actions – These bits determine the action taken when a parity or
framing error is received.
Following the generation of a break-exception interrupt, a receive exception inter-
rupt is generated with RET bit (RISRl[7]) set, when the end of break is detected. The
RET interrupt must be enabled in IER[5] to enable this feature.
When ParMrk = 1 and ParInt = 1, each occurrence of FF hex in the data stream is
preceded by FF hex to distinguish it from a parity error sequence.
8.2.8
Channel Option Register 7 (COR7) — Async Mode Only
CR is defined as 0D hex, NL as 0A hex and NULL as 00 hex.
Bit 7
IStrip – when this bit is set, the most-significant bit of receive characters is stripped,
leaving 7-bit characters. IStrip is applied after all other character processing, but
before special character processing.
Bit 6
LNext – this bit enables the LNext option
0 = All receive characters are processed for special character detection.
1 = The character following the LNext character is not processed for special charac-
ter matching or flow control.
This provides a mechanism to transfer flow control and special characters as normal
data, without invoking flow control action in the CD2231, and without generating
special interrupts. The LNext character is defined in the LNXT register, and when
processed, is always passed to the host CPU as normal data.
Bit 5
Flow control on error characters
0 = Characters received with an error are not processed for special character/flow
control matching.
ParMrk
INPCK
ParInt
0
Generated an exception interrupt
0
1
Translated to a NULL character
01
0
Ignore error; character passed on as good
data
0
1
Discard error character
1
0
Reserved
10
1
Translate to a sequence of FF NULL and the
error character and pass on as Good Data
1
0
Reserved
1
Reserved
Register Name: COR7
Register Description: Channel Option Register 7
Default Value: x’00
Access: Byte Read/Write
Intel Hex Address: x’04
Motorola Hex Address: x’07
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IStrip
LNE
FCErr
0
ONLCR
OCRNL
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