Debug Support
8-2
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
8.1
About debug support
The ARM940T debug interface is based on
IEEE Std. 1149.1- 1990, Standard Test
Access Port and Boundary-Scan Architecture
. See this standard for an explanation of
the terms used in this chapter and for a description of the TAP controller states.
The ARM940T contains hardware extensions for advanced debugging features to
simplify the development of application software, operating systems, and hardware.
The debug extensions allow the core to be stopped by one of the following:
a given instruction fetch (breakpoint)
a data access (watchpoint)
asynchronously by a debug request.
When this happens, the ARM940T is said to be in
debug state
. At this point, the internal
state of the core and the external state of the system can be examined. When
examination is complete, the core and system state can be restored and program
execution resumed.
The ARM940T is forced into debug state either by a request on one of the external
debug interface signals, or by an internal functional unit known as the EmbeddedICE
unit. In debug state, the core isolates itself from the memory system. The core can then
be examined while all other system activity continues as normal.
You can examine the internal state of the ARM940T using a JTAG-style serial interface.
This allows instructions to be serially inserted into the core pipeline without using the
external data bus. So, when in debug state, you can insert a
Store Multiple
(
STM
) into the
instruction pipeline to export the contents of the ARM9TDMI registers. This data can
be serially shifted out without affecting the rest of the system.