Debug Support
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
8-17
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the
SHIFT-DR state, test data is shifted into the bypass register using
TDI
and out using
TDO
after a delay of one
TCK
cycle. The first bit shifted out is a zero.
The bypass register is not affected in the UPDATE-DR state.
CLAMPZ (1001)
This instruction connects a 1-bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the CLAMPZ instruction is loaded into the instruction register and scan chain 0
is selected, all the tristate outputs (as described above) are placed in their inactive state,
but the data supplied to the outputs is derived from the scan cells. The purpose of this
instruction is to ensure that, during production test, each output can be disabled when
its data value is either a logic 0 or logic 1.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register.
In the SHIFT-DR state, test data is shifted into the bypass register using
TDI
and out
using
TDO
after a delay of one
TCK
cycle. The first bit shifted out is a zero.
The bypass register is not affected in the UPDATE-DR state.
SAMPLE/PRELOAD (0011)
When the instruction register is loaded with the SAMPLE/PRELOAD instruction, all
the scan cells of the selected scan chain are placed in the normal mode of operation.
In the CAPTURE-DR state, a snapshot of the signals of the boundary scan is taken on
the rising edge of
TCK
. Normal system operation is unaffected.
In the SHIFT-DR state, the sampled test data is shifted out of the boundary scan using
the
TDO
pin, while new data is shifted in using the
TDI
pin to preload the boundary
scan parallel input latch. This data is not applied to the system logic or system pins
while the SAMPLE/PRELOAD instruction is active.
This instruction must be used to preload the boundary scan register with known data
prior to selecting INTEST or EXTEST instructions.
RESTART (0100)
This instruction is used to restart the processor on exit from debug state. The RESTART
instruction connects the bypass register between
TDI
and
TDO
and the TAP controller
behaves as if the BYPASS instruction had been loaded. The processor resynchronizes
back to the memory system when the RUN-TEST/IDLE state is entered.