Introduction
1-2
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
1.1
About the ARM940T
The ARM940T is a member of the ARM9TDMI family of general-purpose
microprocessors. This family includes:
ARM9TDMI, the core
ARM940T, the core plus cache and protection unit
ARM920T, the core plus cache and MMU.
The ARM9TDMI processor core is a Harvard architecture device implemented using a
five-stage pipeline consisting of Fetch, Decode, Execute, Memory, and Write stages. It
can be provided as a standalone core that can be embedded into more complex devices.
The standalone core has a simple bus interface that allows you to design your own
caches and memory systems around it.
The ARM9TDMI family of microprocessors supports both the 32-bit ARM and 16-bit
Thumb instruction sets, allowing you to trade off between high performance and high
code density.
The ARM940T processor has a Harvard cache architecture with separate 4KB
instruction and 4KB data caches, each with a 4-word line length. A protection unit
allows you to define eight regions of memory for data and eight regions for instructions,
each with individual cache and write buffer configurations and access permissions. The
cache system is software configurable to provide highest average performance or to
meet the requirements of real-time systems. Software configurable options include:
random or round-robin replacement algorithm
write-through or write-back cache operation (independently selectable for each
memory region)
cache locking with granularity 1/64th of cache size.
The cache and write buffers improve CPU performance and minimize accesses to the
AMBA bus and to any off-chip memory, reducing overall system power consumption.
The ARM940T supports the ARM debug architecture and includes logic to assist in
both hardware and software debug. The ARM940T also includes support for
coprocessors, providing access to the instruction and data buses and handshaking
signals.
The ARM940T interface to the rest of the system is over unified address and data buses.
This interface enables implementation of either an
Advanced Microcontroller Bus
Architecture
(AMBA)
Advanced System Bus
(ASB) or
Advanced High-performance
Bus
(AHB) bus scheme with the ARM940T ASB to AHB bridge block available from
ARM Ltd. You can implement an ASB scheme either as a fully-compliant AMBA bus
master, or as a slave for production test. The ARM920T also has a
Tracking ICE
mode
that allows an approach similar to a conventional ICE mode of operation.