Bus Interface Unit
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
6-3
6.2
ASB transfers
The AMBA ASB specification describes three transfer types that are encoded in
BTRAN[1:0]
. Table 6-1 on page 6-3 shows these transfer types.
The output signals
ASTB
,
BURST[1:0]
,
NCMAHB
, and
BUFFSTRAHB
have been
added to the ARM940T bus interface. These are necessary to support the AMBA AHB
wrapper, but can also be used to provide optimized accesses in an AMBA ASB system:
ASTB
This signal distinguishes between an IDLE cycle and the A-TRAN cycle
of a nonsequential transfer. It is asserted with the same timing as
AOUT[31:0]
, changing in phase 2. Usually a memory controller only
commits to a transfer when it sees the S-TRAN cycle, perhaps only
decoding the address during the A-TRAN cycle.
ASTB
is asserted in the
preceding A-TRAN cycle, indicating that the current A-TRAN is
followed by an S-TRAN, providing
AGNT
is HIGH on the next rising
edge of
BCLK
.
BURST[1:0]
Burst transfers are used for cache linefills, and for buffered writes caused
by cache lines that have been evicted or cleaned. In each case, a transfer
of four words takes place.
Table 6-1 AMBA ASB transfer types
BTRAN[1:0]
Transfer type
Description
00
Address-only
(A-TRAN)
Used when no data movement is required. The three
main uses for address-only transfers are:
for IDLE cycles
for bus handover cycles
for speculative address decoding without
committing to a data transfer.
01
-
Reserved.
10
Nonsequential
(N-TRAN)
Used for single transfers or the first transfer of a burst.
The address of the transfer is unrelated to the previous
bus access.
11
Sequential
(S-TRAN)
Used for successive transfers in burst. The address of a
SEQUENTIAL transfer is always related to the
previous transfer.