Caches and Write Buffer
4-12
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
4.4
The write buffer
The ARM940T provides a write buffer to improve system performance. The write
buffer can buffer up to eight words of data at up to four nonsequential addresses. The
write buffer is used for memory that is marked as one of the following:
NCB
WB
WT.
Write buffer behavior is controlled by the protection region attributes of the store being
performed and the DCache and control bits (GCd and GBd) from the protection unit.
These control bits are generated as follows:
GCd bit
The GCd bit is generated from the cachable attribute of the
protection region AND the DCache enable AND the protection
unit enable.
GBd bit
The GBd bit is generated from the bufferable attribute for the
protection region AND the protection unit enable.
All accesses are initially noncachable and nonbufferable until the protection unit has
been programmed and enabled. It follows that the write buffer cannot be used while the
protection unit is disabled.
On reset, the buffer is flushed.
4.4.1
Write buffer operation
The write buffer is used when the DCache hits and/or misses, depending on the mode
of operation. Table 4-2 on page 4-12 shows how the GCd and GBd bits control the
behavior of the write buffer.
Table 4-2 Data write modes
GCd
GBd
Access mode
0
0
NCNB (Noncachable, nonbufferable).
Reads and writes are not cached. They always perform accesses on the AMBA ASB
interface.
Writes are not buffered. The CPU halts until the write is completed on the AMBA
ASB interface.
Reads and writes can be externally aborted.
Cache hits never occur under normal operation.