Caches and Write Buffer
4-18
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
The only significant difference between the sequence of operations for the Dcache and
ICache is that an
MCR
instruction must be used to force the linefill in the ICache, instead
of an
LDR
. This is because of the Harvard nature of the processor. During the
MCR
, the
value set up in the pointer register is output on the instruction address bus, and a
memory access is forced. Because this misses in the cache, as a result of earlier flushing,
a linefill occurs.
The rest of the sequence of operations is exactly the same as for DCache lockdown.
The
MCR
to perform the ICache lookup is a CP15 register 7 operation:
MCR p15,0,Rd,c7,c13,1
A subroutine used to lockdown code in the instruction cache is given in Example 4-2
on page 4-18.
Example 4-2 ICache lockdown subroutine
;
;
;
;
;
;
;
Subroutine lock_i_cache
r1 contains start address of code to be locked down
The subroutine performs a lock-down of instructions in the
I Cache. It first reads the current lock_down index and then
locks down the number of lines requested.
;
;
;
;
;
;
;
;
Note that this subroutine must be located in a noncachable
region of memory to work, or these instructions
themselves will be locked into the cache. Interrupts must
also be disabled.
The subroutine must be called using the ‘BL’ instruction.
This subroutine returns the next free cache line number in
r0, or 0 in r0 if an error occurs.
lock_i_cache
STMFD r13!, {r1-r3}
BIC r1, r1, #0x3f
MRC p15, 0, r3, c9, c0, 1
AND r2, r2, #0x3f
ADD r3, r2, r0
CMP r3, #0x3f
; save corrupted registers
; align address to cache line
; get current instruction cache index
; mask off unwanted bits
; Check to see if current index
; plus line count is greater than 63
; If so, branch to error as
; more lines are being locked down
; than permitted
BGT error
ORR r2, r2, #0x80000000
; set lock bit, r2 contains the cache
; line number to lockdown