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Debug Support
8-48
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
8.14
Debug communications channel
The ARM940T EmbeddedICE unit contains a communication channel for passing
information between the target and the host debugger. This is implemented as
coprocessor 14.
The communications channel consists of:
a 32-bit comms data read register
a 32-bit wide comms data write register
a 6-bit comms control register for synchronized handshaking between the
processor and the asynchronous debugger.
These registers are placed in fixed locations in the EmbeddedICE unit register map (as
shown in Figure 8-1 on page 8-3) and are accessed from the processor using
MCR
and
MRC
instructions to coprocessor 14.
8.14.1
Debug comms channel registers
The debug comms control register is read only. It controls synchronized handshaking
between the processor and the debugger. The format of the debug comms channel
registers is shown in Figure 8-15 on page 8-48.
Figure 8-15 Debug comms control register
The function of each register bit is described below:
Bits 31:28
Contain a fixed pattern that denotes the EmbeddedICE unit
version number, in this case 0010.
Bits 27:2
Unused.
Bit 1
Denotes if the comms data write register is free, as seen by the
processor. If, from the point of view of the processor, the comms
data write register is free (W=0), new data can be written. If it is
not free (W=1), the processor must poll until W=0. If, from the
point of view of the debugger, W=1, some new data has been
written that can then be scanned out.
31 30 29 28 27
2 1 0
R
0
W
0
0 1