Debug Support
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
8-43
Figure 8-11 Watchpoint control register for instruction comparison
The control register bits have the functions shown in Table 8-12 on page 8-43 for
instruction comparison.
7
6
5
4
3
2
1
0
ENABLE
RANGE
CHAIN
EXTERN
InTRANS
0
X
X
ITBIT
8
Table 8-12 Watchpoint control register for instruction comparison
Bit
Function
ITBIT
Compares against the Thumb state signal from the core to determine between a
Thumb (
ITBIT
= 1) instruction fetch or an ARM (
ITBIT
= 0) fetch.
InTRANS
Compares against the not translate signal from the core to determine between a
User mode (
InTRANS
= 0) instruction fetch, and a privileged mode
(
InTRANS
= 1) fetch.
EXTERN
Is an external input into the EmbeddedICE unit that allows the watchpoint to be
dependent on some external condition. The
EXTERN
input for watchpoint 0 is
labelled
EXTERN0
, and the
EXTERN
input for watchpoint 1 is labeled
EXTERN1
.
CHAIN
Can be connected to
CHAIN
output of another watchpoint to implement, for
example, debugger requests of the form
breakpoint on address YYY only when
in process XXX
.
In the ARM940T EmbeddedICE unit, the
CHAINOUT
output of watchpoint 1
is connected to the
CHAIN
input of watchpoint 0. The
CHAINOUT
output is
derived from a latch. The address/control field comparator drives the write
enable for the latch, and the input to the latch is the value of the data field
comparator. The
CHAINOUT
latch is cleared when the control value register
is written, or when
nTRST
is LOW.
RANGE
Can be connected to the range output of another watchpoint register. In the
ARM940T EmbeddedICE unit, the
RANGEOUT
output of watchpoint 1 is
connected to the
RANGE
input of watchpoint 0. This allows two watchpoints
to be coupled for detecting conditions that occur simultaneously, for example,
for range-checking.
ENABLE
If a watchpoint match occurs, the
IBREAKPT
or
DBREAKPT
signal is only
asserted when the ENABLE bit is set. This bit only exists in the value register.
It cannot be masked.