Programmer
’
s Model
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
2-7
Instructions
CDP
,
LDC
, and
STC
, together with unprivileged
MRC
and
MCR
instructions to
CP15, cause the undefined instruction trap to be taken. The
CRn
field of
MRC
and
MCR
instructions specifies the coprocessor register to access. The
CRm
field and
opcode_2
fields specify a particular action when addressing registers. The L bit distinguishes
between an
MRC
(L=1) and an
MCR
(L=0).
Note
Attempting to read from a nonreadable register, or to write to a nonwritable register
causes unpredictable results.
The
opcode_1
,
opcode_2
, and
CRm
fields should be zero, except when the values specified
are used to select the desired operations, in all instructions that access CP15. Using
other values results in unpredictable behavior.
2.3.2
Register 0, ID code
This is a read-only register that returns a 32-bit device ID code. You can access the ID
code register by reading CP15 register 0 with the
opcode_2
field set to any value other
than 1. For example:
MRC cp15, 0, rd, c0, c0,{0,2-7}; returns ID register
The contents of the ID code are shown in Table 2-4 on page 2-7.
2.3.3
Register 0, cache type
This is a read-only register that contains information about the size and architecture of
the
Instruction Cache
(ICache) and
Data Cache
(DCache), allowing operating systems
to establish how to perform such operations as cache cleaning and lockdown. All
ARMv4T and later cached processors contain this register, allowing RTOS vendors to
produce future-proof versions of their operating systems.
Table 2-4 ID code register
Register bits
Function
Value
31:12
Implementer
0x41
(identifies ARM)
23:16
Architecture version
0x2
15:4
Part number
0x940
3:0
Layout revision
Revision