ARM940T Signal Descriptions
A-4
Copyright 199, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
A.2
Coprocessor interface signals
Table A-2 on page A-4 describes the coprocessor interface signals.
For more information on the coprocessor interface see Chapter 7
Coprocessor
Interface
.
Table A-2 Coprocessor interface signals
Name
Direction
Description
CHSDE[1:0]
Input
Coprocessor handshake decode. The handshake signals from the Decode stage of
the coprocessor pipeline follower.
CHSEX[1:0]
Input
Coprocessor handshake execute. The handshake signals from the Execute stage of
the coprocessor pipeline follower.
CPCLK
Output
Coprocessor clock. This clock controls the operation of the coprocessor interface.
CPDOUT[31:0]
Output
Coprocessor data out. The coprocessor data bus for transferring
MCR
and
LDC
data to
the coprocessor.
CPDIN[31:0]
Input
Coprocessor data in. The coprocessor data bus for transferring
MRC
and
STC
data from
the coprocessor to the ARM940T.
CPID[31:0]
Output
Coprocessor instruction data. This is the coprocessor instruction data bus that
instructions are transferred over to the pipeline follower in the coprocessor.
CPLATECANCEL
Output
Coprocessor late cancel. When a coprocessor instruction is being executed, if this
signal is HIGH during the first memory cycle, the coprocessor instruction is
canceled without updating the coprocessor state.
nCPMREQ
Output
Not coprocessor memory request. When LOW on a rising
CPCLK
edge and
nCPWAIT
LOW, the instruction on
CPID
enters the coprocessor pipeline follower
Decode stage. The second instruction previously in the pipeline follower Decode
stage enters its Execute stage.
CPPASS
Output
Coprocessor pass. This signal indicates that there is a coprocessor instruction in the
Execute stage of the pipeline, and it must be executed.
CPTBIT
Output
Coprocessor thumb bit. If HIGH, the coprocessor interface is in Thumb state.
nCPTRANS
Output
Not coprocessor translate. When HIGH, the coprocessor interface is in a
non-privileged mode. When LOW, the coprocessor interface is in a privileged
mode. The coprocessor samples this signal on every cycle when determining the
coprocessor response.
nCPWAIT
Output
Not coprocessor wait. The coprocessor clock
CPCLK
is qualified by
nCPWAIT
to
allow the ARM940T to control the transfer of data on the coprocessor interface.
nCPWAIT
changes while
CPCLK
is HIGH.