Programmer
’
s Model
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
2-15
2.3.8
Register 5, instruction and data space protection registers
These registers contain the access permission bits for the instruction and data protection
regions. The
opcode_2
field determines if the instruction or data access permissions are
programmed:
If the
opcode_2
field = 0, the data space bits are programmed. For example:
MCR p15,0,Rd,c5,co,0
; Write data space access permissions
MRC p15,0,Rd,c5,co,0
; Read data space access permissions
If the
opcode_2
field =1, the instruction space bits are programmed. For example:
MCR p15,0,Rd,c5,co,1
; Write instruction space access permissions
MRC p15,0,Rd,c5,co,1
; Read instruction space access permissions
Each register contains the access permission bits, apn[1:0], for the eight areas of
instruction or data memory, as shown in Table 2-13 on page 2-15.
The values of the Iapn[1:0] and Dapn[1:0] bits define the access permission for each
area of memory. The access encoding is shown in Table 2-14 on page 2-16.
Note
On reset, the values of the Iapn[1:0] and Dapn[1:0] bits for all areas are undefined.
However, on reset, the protection unit is disabled and all areas are effectively set to
no
access
. Therefore, you must program the protection space registers before you enable
the protection unit.
Table 2-13 Protection space register format
Register bit
Function
15:14
ap7[1:0] bits of area 7
13:12
ap6[1:0] bits of area 6
11:10
ap5[1:0] bits of area 5
9:8
ap4[1:0] bits of area 4
7:6
ap3[1:0] bits of area 3
5:4
ap2[1:0] bits of area 2
3:2
ap1[1:0] bits of area 1
1:0
ap0[1:0] bits of area 0