ARM940T Signal Descriptions
ARM DDI 0144B
Copyright 199, 2000 ARM Limited. All rights reserved.
A-5
A.3
JTAG and TAP controller signals
Table A-3 on page A-5 describes the JTAG and TAP controller signals.
Table A-3 JTAG and TAP controller signals
Name
Direction
Description
DRIVEOUTBS
Output
Boundary scan cell enable. This signal is used to control the multiplexors in the
scan cells of an external boundary scan chain. This signal changes in the
UPDATE-IR state when scan chain 3 is selected, and either the INTEST, EXTEST,
CLAMP, or CLAMPZ instruction is loaded. When an external boundary scan
chain is not connected, this output must be left unconnected.
ECAPCLKBS
Output
EXTEST capture clock for boundary scan. This is a
TCK2
wide pulse generated
when the TAP controller state machine is in the CAPTURE-DR state, the current
instruction is EXTEST, and scan chain 3 is selected. This signal is used to capture
the chip level inputs during EXTEST. When an external boundary scan chain is not
connected, this output must be left unconnected.
ICAPCLKBS
Output
INTEST capture clock. This is a
TCK2
wide pulse generated when the TAP
controller state machine is in the CAPTURE-DR state, the current instruction is
INTEST, and scan chain 3 is selected. This signal is used to capture the chip level
outputs during INTEST. When an external boundary scan chain is not connected,
this output must be left unconnected.
IR[3:0]
Output
Tap controller instruction register. These four bits reflect the current instruction
loaded into the TAP controller instruction register. The bits change on the falling
edge of
TCK
when the state machine is in the UPDATE-IR state.
PCLKBS
Output
Boundary scan update clock. This is a
TCK2
wide pulse generated when the TAP
controller state machine is in the UPDATE-DR state, and scan chain 3 is selected.
This signal is used by an external boundary scan chain as the update clock. When
an external boundary scan chain is not connected, this output must be left
unconnected.
RSTCLKBS
Output
Boundary scan reset clock. This signal denotes that either the TAP controller state
machine is in the RESET state, or that
nTRST
has been asserted. This can be used
to reset external boundary scan cells.
SCREG[4:0]
Output
Scan chain register. These four bits reflect the ID number of the scan chain
currently selected by the TAP controller. These bits change on the falling edge of
TCK
when the TAP state machine is in the UPDATE-DR state.
SDIN
Output
Boundary scan serial input data. This signal contains the serial data to be applied
to an external scan chain, and is valid around the falling edge of
TCK
.