Index
Index-2
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
Debug
debug scan chain 8-21
entered from Thumb state 8-29
hardware extensions 8-2, 8-4
instruction register 8-13
scan chains 8-21
speed 8-30
state-machine controller 8-13
Debug interface
standard 8-2
TAP controller states 8-2
Debug state 8-2
Debug system 8-3
Dirty data eviction 6-13
E
EmbeddedICE 8-2, 8-5, 8-10, 8-39
accessing hardware registers 8-22
hardware 8-39
single stepping 8-47
EmbeddedICE watchpoint units
debugging 8-11
programming 8-11
testing 8-11
External scan chains 8-20
F
FastBus mode 5-3
Functional block diagram 1-3
I
Implementation options 2-3
Instruction cycle
counts and bus activity 11-3
data bus instruction times 11-5
Interlocks
LDM dependent timing 11-10
LDM timing 11-8
single load timing 11-6
two cycle load timing 11-7
Interlocks, pipeline 11-6
J
JTAG interface 8-13, 8-28
L
Line length encoding 2-11
M
Memory clock 8-27
N
Nonbuffered STR 6-8, 6-9
Noncached fetches 6-5
Noncached LDM 6-6
Noncached LDRs 6-5
O
Options, implementation 2-3
P
Pipeline
interlocks 11-6
Pipeline interlocks 7-11
Processor state, determining 8-29
Programmer
s model 2-1
R
Register map
CP15 2-5
S
Scan chains 8-21
external 8-20
scan chain 0 bit order 10-1
scan chain 2 8-22
Serial test and debug 8-12
Single stepping 8-47
Slave transfers 6-16
Swap 6-14
Synchronous mode 5-4
System speed
instructions 8-31
System state
control 8-30
T
TAP controller 8-2, 8-11, 8-12, 8-20
TAP state machine 8-27
Test
support 10-1
system reset 8-28
Test data registers 8-18
Testing
test patterns 10-2
Transfer types, ASB 6-3
W
Watchpoints
timing 8-7
Write-back 6-13