Bus Interface Unit
6-4
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
These signals indicate a sequential burst, as shown in Table 6-2 on
page 6-4.
The
BURST[1:0]
signals change in phase 2 and are asserted in the phase
when
ASTB
is asserted.
BURST[1:0]
then remain unchanged until the
next transfer.
BURST[1:0]
only indicates a four-word transfer when either a cache
linefill takes place, or when a dirty line within a write back protection
region has been evicted. In all other circumstances,
BURST[1:0]
indicates single word transfers. This is true for
LDM
and
STM
instructions,
regardless of the number of registers being transferred.
BURST[1:0]
can be factored into both the arbiter and decoder of the
AMBA system, and can be used to prevent a new bus master taking
control of the ASB, giving a more efficient transfer.
NCMAHB
This signal indicates for noncached load multiples and store multiples
whether more words are requested as part of the current burst transfer.
When HIGH this indicates more words are requested. When LOW, on the
last S-TRAN of the burst, this indicates that the current transfer is the last
word of the burst. It is asserted in phase 2 and is only valid if
AGNT
remains asserted throughout the transfer.
BUFFSTRAHB
This signal indicates when the NCMAHB signal is set but not valid. This
can happen when some buffered stores are occuring.
Table 6-2 Burst transfers
BURST[1:0]
Transfer
00
No sequential information available (default)
01
Reserved
10
Current access is part of a four-word transfer
11
Reserved