![](http://datasheet.mmic.net.cn/360000/ARM940T_datasheet_16606732/ARM940T_20.png)
Programmer’s Model
2-2
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
2.1
About the programmer
’
s model
The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor
core, instruction and data caches, a write buffer, and a protection unit for defining the
attributes of regions of memory.
The programmer
’
s model of the ARM940T consists of the programmer
’
s model of the
ARM9TDMI (see
About the ARM9TDMI programmer
’
s model
on page 2-3) with the
following additions and modifications:
The ARM940T incorporates two coprocessors:
—
CP14, which allows software access to the debug communications channel.
You can access the registers defined in CP14 using
MCR
and
MRC
instructions.
These are described in
Accessing CP15 registers
on page 2-6.
—
CP15, the system control coprocessor, which provides additional registers
that are used to configure and control the caches, protection unit, and other
system options of the ARM940T, such as big or little-endian operation. You
can access the registers defined in CP15 using
MCR
and
MRC
instructions.
These are described in
Accessing CP15 registers
on page 2-6.
The ARM940T also features an external coprocessor interface that allows the
attachment of a closely-coupled coprocessor on the same chip, for example, a
floating point unit. You can access registers and operations provided by any
coprocessors attached to the external coprocessor interface using appropriate
coprocessor instructions.
Memory accesses for instruction fetches, and data loads and stores can be cached
or buffered. Cache and write buffer configuration and operation is described in
detail in Chapter 4
Caches and Write Buffer
.