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Caches and Write Buffer
4-16
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
4.5
Cache lockdown
To provide predictable code behavior in embedded systems, a mechanism for locking
code and data into the ICache and DCache respectively is provided. For example, this
feature can be used to hold high-priority interrupt routines where there is a hard
real-time constraint, or to hold the coefficients of a DSP filter routine to reduce external
bus traffic.
Locking down a region of the ICache or DCache is achieved by executing a short
software routine, taking note of these requirements:
the program must be held in a noncachable area of memory
the cache must be enabled and interrupts must be disabled
software must ensure that the code or data to be locked down is not already in the
cache
if the caches have been used after the last reset, the software must ensure that the
cache in question is cleaned, if appropriate, and then flushed.
Lockdown in the DCache is achieved through use of CP15 register 9. ICache lockdown
uses both CP15 registers 7 and 9.
As described in
Cache architecture
on page 4-2, the ARM940T ICache and DCache
each comprise four segments. Each cache segment comprises 64 lines of four words.
Each segment is 1KB in size. Lockdown can be performed with a granularity of one line
across each of the four segments. The smallest space that can be locked down is 16
words. Lockdown starts at line zero, and can continue until up to 63 of the 64 lines are
locked.
4.5.1
Locking down the caches
The procedures for locking down a line in the ICache and in the DCache are slightly
different. In both cases:
1.
The cache must be put into lockdown mode by programming register 9.
2.
A linefill must be forced.
3.
The corresponding data must be locked in the cache.
If more than one line is to be locked, a software loop must repeat this procedure.