Debug Support
8-22
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
This scan chain is 67 bits long, 32 bits for data values, 32 bits for instruction data, and
3 control bits, SYSSPEED, WPTANDBKPT, and
DDEN
. The three control bits serve
four different purposes:
Under normal INTEST test conditions, the
DDEN
signal can be captured and
examined.
During EXTEST test conditions, a known value can be scanned into
DDEN
to be
driven into the rest of the system. If a logic 1 is scanned into
DDEN
, the data data
bus
DD[31:0]
drives out the values stored in its scan cells. If a logic 0 is scanned
into
DDEN
,
DD[31:0]
captures the current input values.
While debugging, the value placed in the SYSSPEED control bit determines if the
ARM9TDMI synchronizes back to system speed before executing the instruction.
After the ARM9TDMI has entered debug state, the first time SYSSPEED is
captured and scanned out, its value tells the debugger if the core has entered
debug state in response to a breakpoint (SYSSPEED LOW), or a watchpoint
(SYSSPEED HIGH). If the instruction directly following one that causes a
watchpoint has a breakpoint set on it, then the WPTANDBKPT bit is set. This
situation does not effect how to restart the code.
Scan chain 2
Purpose
Allows access to the EmbeddedICE unit registers. The order of
the scan chain from
TDI
to
TDO
is shown in Table 8-4 on
page 8-22.
Length
38 bits
To access this serial register, scan chain 2 must first be selected using the SCAN_N TAP
controller instruction. The TAP controller must then be placed in INTEST mode.
No action is taken during CAPTURE-DR.
Table 8-4 Scan chain 4 addressing mode bit order
Bits
Contents
37
Read = 0
Write = 1
36:32
EmbeddedICE register address
31:0
Data