Debug Support
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
8-29
8.8
Determining the core and system state
You can examine the core and system state when the ARM940T is in debug state. You
do this by forcing load and store multiples into the pipeline.
Before the core and system state can be examined, the debugger must first determine if
the processor has entered debug from Thumb or ARM state. This is achieved by
examining bit 4 of the EmbeddedICE unit debug status register. If this is HIGH, debug
has been entered from Thumb state.
8.8.1
Determining the core state
If the processor has entered debug state from Thumb state, the simplest course of action
is for the debugger to force the core back into ARM state. When this is done, the
debugger can always execute the same sequence of instructions to determine the
processor state.
To force the processor into ARM state, the following sequence of Thumb instructions
must be executed on the core:
STR r0, [r1]
MOV r0, PC
STR r0, [r1]
BX PC
MOV r8, r8
MOV r8, r8
; Save r0 before use
; Copy PC into R0
; Save the PC in R0
; Jump into ARM state
; NOP
; NOP
The above use of R1 as the base register for the stores is for illustration only. Any
register can be used.
Because all Thumb instructions are only 16 bits long, the simplest course of action when
shifting them into scan chain 1 is to repeat the instruction twice on the instruction data
bus bits. For example, the encoding for
BX r0
is
0x4700
. If
0x47004700
is shifted into the
32 bits of the instruction data bus of scan chain 1, then the debugger does not have to
keep track of the half of the bus that the processor expects to use to read instructions.
From this point on, the processor state can be determined by the sequences of ARM
instructions described below.
When the processor is in ARM state, typically the first instruction executed is:
STMIA r0, {r0-r15}
This causes the contents of the registers to be made visible on the data data bus. These
values can then be sampled and shifted out.