Glossary
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
Glossary-3
Condition field
A 4-bit field in an instruction that is used to specify a codition under which the
instruction can execute.
Content addressable
memory
Memory that is identified by its contents. Content addressable memory is used in
CAM-RAM architecture caches to store the tags for cache entries.
Coprocessor
A processor that supplements the main CPU. It carries out additional functions that the
main CPU cannot perform. Usually used for floating-point math calculations, signal
processing, or memory management.
CPU
See
Central Processing Unit
.
Data Abort
An indication from a memory system to a core that it should halt execution of an
attempted illegal memory access. A data abort is attempting to access invalid data
memory. See also
Abort
,
External abort
and
Prefetch abort
.
Data cache
See
DCache
.
DCache
A block of on-chip fast access memory locations, situated between the processor and
main memory, used for storing and retreiving copies of often used data. This is done to
greatly reduce the average speed of memory accesses and so to increase processor
performance.
Debugger
A debugging system that includes a program, used to detect, locate, and correct
software faults, together with custom hardware that supports software debugging.
Domain
A collection of sections, large pages and small pages of memory, which can have their
access permissions switched rapidly by writing to the Domain Access Control Register
(CP15 register 3).
Double word
A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise
stated.
EmbeddedICE
The additional JTAG-based hardware provided by debuggable ARM processors to aid
debugging.
Endianness
Byte ordering. The scheme that determines the order in which successive bytes of a data
word are stored in memory. See also
Little-endian
and
Big-endian
.
Exception vector
One of a number of fixed addresses in low memory, or in high memory if high vectors
are configured, that contains the first instruction of the corresponding interrupt service
routine.
External abort
An indication from an external memory system to a core that it should halt execution of
an attempted illegal memory access. An external abort is caused by the external
memory system as a result of attempting to access invalid memory. See also
Abort
,
Data abort
and
Prefetch abort
Halfword
A 16-bit data item.