ARM940T Signal Descriptions
A-8
Copyright 199, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
A.4
Debug signals
Table A-4 on page A-8 describes the debug signals.
Table A-4 Debug signals
Name
Direction
Description
COMMRX
Output
Communications channel receive. When HIGH, this signal denotes that the
comms channel receive buffer contains data waiting to be read by the processor
core.
COMMTX
Output
Communications channel transmit. When HIGH, this signal denotes that the
comms channel transmit buffer is empty.
DBGACK
Output
Debug acknowledge. When HIGH, this signal indicates the ARM is in debug state.
DBGEN
Input
Debug enable. This input signal allows the debug features of the ARM940T to be
disabled. This signal must be HIGH unless debugging is not required.
DBGRQI
Output
Internal debug request. This signal represents the debug request signal presented
to the processor core. This is a combination of
EDBGRQ
, as presented to the
ARM940T, and bit 1 of the debug control register.
DEWPT
Input
External watchpoint. This signal allows external data watchpoints to be
implemented.
ECLK
Output
External clock output.
EDBGRQ
Input
External debug request. When driven HIGH, this causes the processor to enter
debug state when execution of the current instruction has completed.
EXTERN0
Input
External input 0. This is an input to watchpoint unit 0 of the EmbeddedICE unit in
the processor, and allows breakpoints/watchpoints to be dependent on an external
condition.
EXTERN1
Input
External input 1. This is an input to watchpoint unit 1 of the EmbeddedICE unit in
the processor, and allows breakpoints/watchpoints to be dependent on an external
condition.
IEBKPT
Input
External breakpoint. This signal allows an external instruction breakpoints to be
implemented.
INSTREXEC
Output
Instruction executed. Indicates that in the previous cycle, the instruction in the
Execute stage of the pipeline passed its condition codes, and executed.