Caches and Write Buffer
4-6
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
You can disable the ICache by clearing bit 12 of the CP15 control register. This has the
effect of preventing all ICache look-ups and linefills, and forces all instruction fetches
to be performed by single external accesses.
4.2.3
ICache validity
The ARM940T does not support external memory snooping. Therefore, if
self-modifying code is written, the instructions in the ICache might become invalid.
Similarly, if the instruction protection regions are reprogrammed, code might exist in
the cache that should be in a noncachable region. In either of these cases, the ICache
must be flushed by the programmer.
You can flush the entire ICache by software in one operation, or you can flush it one
line at a time by writing to the CP15 cache operations register (register 7). The ICache
is automatically flushed during reset. The ICache never has to be cleaned because its
only source of data is from external memory. The processor only ever performs reads
from the ICache.
Flushing the entire cache
As shown in Table 2-19 on page 2-19, you can flush the entire ICache using an
MCR
instruction. In this case, the contents of the ARM register transferred to CP15 should be
zero. The code segment shown below can be used. The use of r0 is arbitrary:
M0V r0,#0
MCR p15,r0,c7,c5,0
; Clear r0
; Flush entire ICache
Flushing the entire cache also flushes any locked down code. If the ICache contains
locked down code, the programmer must flush lines individually, avoiding the lines
used for the locked down code.
Flushing a single cache line
Single cache lines can be flushed. To do this, the cache line must be specified in Rd. The
ARM940T ICache comprises four segments, each with 64 lines, which means that both
the segment and line number index must be specified.