Contents
iv
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
Chapter 4
Caches and Write Buffer
4.1
Cache architecture ..................................................................................... 4-2
4.2
ICache ........................................................................................................ 4-5
4.3
DCache ....................................................................................................... 4-8
4.4
The write buffer ......................................................................................... 4-12
4.5
Cache lockdown ....................................................................................... 4-16
Chapter 5
Clock Modes
5.1
5.2
5.3
5.4
About ARM940T clocking ........................................................................... 5-2
FastBus mode ............................................................................................ 5-3
Synchronous mode ..................................................................................... 5-4
Asynchronous mode ................................................................................... 5-6
Chapter 6
Bus Interface Unit
6.1
About the ARM940T bus interface ............................................................. 6-2
6.2
ASB transfers ............................................................................................. 6-3
6.3
External aborts ......................................................................................... 6-17
6.4
Memory access order ............................................................................... 6-18
Chapter 7
Coprocessor Interface
7.1
About the coprocessor interface ................................................................. 7-2
7.2
LDC or STC ................................................................................................ 7-5
7.3
MCR/MRC .................................................................................................. 7-9
7.4
Interlocked MCR ....................................................................................... 7-11
7.5
CDP .......................................................................................................... 7-13
7.6
Privileged instructions ............................................................................... 7-15
7.7
Busy-waiting and interrupts ...................................................................... 7-17
Chapter 8
Debug Support
8.1
About debug support .................................................................................. 8-2
8.2
Debug systems ........................................................................................... 8-3
8.3
Debug interface signals .............................................................................. 8-5
8.4
Scan chains and JTAG interface .............................................................. 8-11
8.5
The JTAG state machine .......................................................................... 8-12
8.6
Test data registers .................................................................................... 8-18
8.7
ARM940T core clocks .............................................................................. 8-27
8.8
Determining the core and system state .................................................... 8-29
8.9
Exit from debug state ................................................................................ 8-33
8.10
The behavior of the program counter during debug ................................. 8-36
8.11
EmbeddedICE unit ................................................................................... 8-39
8.12
Vector catching ......................................................................................... 8-46
8.13
Single-stepping ......................................................................................... 8-47
8.14
Debug communications channel .............................................................. 8-48
8.15
The debugger view of the cache .............................................................. 8-52